6.8.1 parameter Statement
The parameter statement allows the designer to give a constant a name. Typical uses are to specify width of registers and delays. For example, the following allows the designer to parameterized the declarations of a model. parameter byte_size = 8;
reg [byte_size - 1:0] A, B;
6.8.2 Continuous Assignment
Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value. The following ands the values on the wires in1 and in2 and drives the wire out. The keyword assign is used to distinguish the continuous assignment from the procedural assignment. See Section 2.3 for more discussion on continuous assignment. assign out = ~(in1 & in2);
6.8.3 …show more content…
The first type is a delay control in which an expression specifies the time duration between initially encountering the statement and when the statement actually executes. The second type of timing control is the event expression, which allows statement execution. The third subsection describes the wait statement which waits for a specific variable to change.
Verilog is a discrete event time simulator, i. e., events are scheduled for discrete times and placed on an ordered-by-time wait queue. The earliest events are at the front of the wait queue and the later events are behind them. The simulator removes all the events for the current simulation time and processes them. During the processing, more events may be created and placed in the proper place in the queue for later processing. When all the events of the current time have been processed, the simulator advances time and processes the next events at the front of the queue.
If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following: 1. gate or wire delay, if